1. Field of the Invention
The present invention relates generally to a memory control device and a memory control method thereof. More particularly, the present invention relates to a memory control device and method which compensates for errors occurring when data is written to a memory and enables a smooth writing operation.
2. Description of the Related Art
A memory includes a recording medium that writes and reads data. A Dynamic Random Access Memory (DRAM) exemplifies such memory and is divided into a single data rate (SDR) memory and a double data rate (DDR) memory according to a data transmission rate per strobe. The SDR memory writes or reads data at a rising edge of a strobe and allows a single time data writing or reading operation per one strobe period.
On the other hand, the DDR memory writes or reads data at both a rising edge and falling edge of a strobe and allows two data writing or reading operations per one strobe period. Therefore, compared to the SDR memory, the DDR memory has a narrow valid data window (VDW) during which the memory writes or reads data smoothly.
In order to write or read data accurately through the narrow VDW, a memory control device is required. The memory control device is embedded in an application specific integrated circuit (ASIC) as shown in FIG. 1.
FIG. 1 is a view illustrating an ASIC 1 having a conventional memory control device.
Referring to FIG. 1, a conventional memory control device 10 is embedded in the ASIC 1 and performs an interfacing between the ASIC 1 and a DDR memory 20. The memory control device 10 comprises a delay compensation circuit (DCC) 11, first clock tree synthesis (CTS) 13, second CTS 15, strobe generator 17 and data generator 19.
The DCC 11 receives a system clock (referred to as ‘SYSTEM CLK’) provided by the ASIC 1 and calculates delay information that is necessary to delay the SYSTEM CLK for one period. When the DDR memory 20 provides a DRAM data strobe (referred to as ‘read_dqs signal’) and a data signal (referred to as ‘read_data signal’), the DCC 11 delays the ‘read_dqs signal’ based on the delay information in order to read the read_data signal at a rising edge and a falling edge of the ‘read_dqs signal’.
The DCC 11 delays a strobe generation control signal (referred to as ‘clk_dqs_out signal’) and a data generation control signal (referred to as ‘clk_wr signal’) that are necessary to generate a strobe signal (referred to as ‘write_dqs signal’) for writing data and generating a data signal (referred to as ‘data_out signal’), respectively, based on the delay information, and the DCC 11 then outputs the delayed signals.
The strobe generator 17 generates the write_dqs signal using a single line clk_dqs_out signal and a single line clk_wr signal. The data generator 19 generates the data_out signal of 8 bits using the eight-line clk_wr signals.
The first CTS 13 comprises a buffer for delaying the clk_dqs_out signal and the clk_wr signal, respectively, such that the clk_dqs_out signal and the clk_wr_signal arrive at the strobe generator 17 with a same phase. That is, the first CTS 13 additionally delays such that the single line clk_dqs_out signal and the single line clk_wr signal output from the DCC 11 have the same phase.
The second CTS 15 comprises a buffer for additionally delaying such that the eight-line clk_wr signals provided by the data generator 19 have the same phase.
Since the clk_dqs_out signal and the clk_wr signal output from the DCC 11 are additionally delayed by the CTS 13 and CTS 15, a VDW of the data_out signal becomes narrowed and a phase difference between the SYSTEM CLK and the write_dqs_out signal becomes larger due to the additional delay.
FIG. 2 is a view illustrating an output signal of the ASIC 1 having the conventional memory control device 10.
FIG. 2 illustrates an example case where the phase of the clk_dqs_out signal output from the DCC 11 is delayed as much as 90°, and the phase of the clk_wr signal output from the DCC 11 is delayed as much as 180°.
The clk_dqs_out signal delayed as much as 90° and the clk_wr signal delayed as much as 180° are additionally delayed by the first CTS 13 and the second CTS 15. The write_dqs signal output from the conventional memory control device 10 has a phase difference of 90° or more in accordance with the SYSTEM CLK which results in a narrow VDW of the data_out signal.
Also, the DDR memory 20 stores data A, B, C, D read at the rising edge and the falling edge of the write_dqs signal. However, since the data A, B, C, D falls outside the VDW, accurate data cannot be obtained
To this end, a writing error is likely to occur in the DDR memory 20. The writing error is more problematic when there are changes in environmental factors, such as voltage, temperature, and noise caused by a transmission channel characteristic. As a result, a smooth writing operation of the DDR memory 20 cannot be achieved due to the additional delay of the first CTS 13 and the second CTS 15.
Accordingly, there is a need for an improved memory control device and method to compensate for errors occurring when data is written to a memory and to enable a smooth writing operation.